Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31440
Change subject: soc/intel/common: Add DP AUX channel control register bits ......................................................................
soc/intel/common: Add DP AUX channel control register bits
This change implements the SOC-specific function for providing the DP AUX channel control register bits.
All of the recent Intel SOCs supported by soc/intel/common use the same format for this register.
Change-Id: I95b75078f907da7df30bda2b3468668a2f0d7a47 Signed-off-by: Duncan Laurie dlaurie@google.com --- M src/drivers/intel/gma/i915_reg.h M src/soc/intel/common/block/graphics/graphics.c 2 files changed, 14 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/31440/1
diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index e0bf142..f32f0cd 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -2323,6 +2323,10 @@ #define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff) #define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
+/* Used by Sky Lake and later SOC */ +#define DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(c) (((c) - 1) << 5) +#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) ((c) - 1) + /* * Computing GMCH M and N values for the Display Port link * diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 19a78e7..a8c93ec 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -20,6 +20,7 @@ #include <device/pci_ids.h> #include <intelblocks/graphics.h> #include <soc/pci_devs.h> +#include <drivers/intel/gma/i915.h>
/* SoC Overrides */ __weak void graphics_soc_init(struct device *dev) @@ -96,11 +97,20 @@ graphics_gtt_write(reg, val); }
+/* Return the SOC-specific bits of the AUX channel control register */ +uint32_t intel_dp_aux_ctl_soc(void) +{ + /* Currently all SOCs supported here use the gen9+ register format */ + return DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | + DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); +} + static const struct device_operations graphics_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = graphics_soc_init, + .ops_i2c_bus = &intel_edp_aux_i2c_bus_ops, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, };