Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36651 )
Change subject: intel/cannonlake: Implement PCIe RP devicetree update
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Patch Set 24: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/36651/24/src/mainboard/google/hatch...
File src/mainboard/google/hatch/variants/duffy/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/36651/24/src/mainboard/google/hatch...
PS24, Line 297: device pci 1c.6 on
What do you mean exactly? HW support? FSP support? coreboot support?
I meant coreboot support like `pcie_rp_update_devicetree`.
Thanks for the background and explanation. I looked through the code and it looks like it should be fine to actually have func0 set to off as you outlined -- at least I don't see a path which would behave differently if that was the case.
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