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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58115
to look at the new patch set (#3).
Change subject: soc/amd/common: Add support to read and set SPI speeds from verstage ......................................................................
soc/amd/common: Add support to read and set SPI speeds from verstage
Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock.
BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I281531e506b56173471b918c746f58d1ad97162c --- M src/soc/amd/common/block/include/amdblocks/psp_efs.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/psp/Makefile.inc M src/soc/amd/common/block/psp/psp_efs.c M src/soc/amd/common/block/spi/fch_spi.c M src/soc/amd/common/psp_verstage/fch.c 6 files changed, 12 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/58115/3