Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48645 )
Change subject: soc/amd/cezanne: Add SMI support ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48645/2/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/48645/2/src/soc/amd/cezanne/include... PS2, Line 79: #define SMITYPE_FAKE_STS0 33 : #define SMITYPE_FAKE_STS1 34 : #define SMITYPE_FAKE_STS2 35
Let's do this like Picasso. Rename 33 for PSP and make the other two reserved.
Done
https://review.coreboot.org/c/coreboot/+/48645/2/src/soc/amd/cezanne/include... PS2, Line 164: # define SMITRIG0_FAKE0 (1 << 25) : # define SMITRIG0_FAKE1 (1 << 26) : # define SMITRIG0_FAKE2 (1 << 27)
Let's do this like in Picasso. Call bit 25 PSP and make the other two reserved.
Done