[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Fix wrong setting of DRS config

[huayang duan (Code Review)]

Hello Duan huayang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/39626

to review the following change.

Change subject: soc/mediatek/mt8183: Fix wrong setting of DRS config
......................................................................

soc/mediatek/mt8183: Fix wrong setting of DRS config

Update setting of DRS config

BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui

Change-Id: Id38fc224b54c3947af8bbc5c1a4a8d70eb53d5fb
Signed-off-by: Huayang Duan 
---
M src/soc/mediatek/mt8183/dramc_pi_basic_api.c
1 file changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/39626/1

diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
index dc3676a..67ed2db 100644
--- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c
@@ -486,9 +486,10 @@

/* DRAM DRS DISABLE */
    	clrsetbits32(&ch[chn].ao.drsctrl,
-			(0x1 << 21) | (0x3f << 12) | (0xf << 8) | (0x1 << 6),
-			(0x1 << 19) | (0x3 << 12) | (0x8 << 8) |
-			(0x3 << 4) | (0x1 << 2) | (0x1 << 0));
+			(0x1 << 0) | (0x1 << 2) | (0x1 << 4) | (0x1 << 5) | (0x1 << 6) |
+			(0xf << 8) | (0x7f << 12) | (0x1 << 19) | (0x1 << 21),
+			(0x1 << 0) | (0x0 << 2) | (0x0 << 4) | (0x1 << 5) | (0x0 << 6) |
+			(0x8 << 8) | (0x3 << 12) | (0x1 << 19) | (0x0 << 21));
    	setbits32(&ch[chn].ao.dummy_rd, 0x3 << 26);
    }
    dramc_dqs_precalculation_preset();