[coreboot-gerrit] Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock

[Angel Pons (Code Review)]

Attention is currently required from: Felix Singer, Jamie Ryu, Subrata Banik, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Tim Wawrzynczak, Paul Menzel, Raj Astekar.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 )

Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
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Patch Set 15:

(2 comments)

File src/soc/intel/meteorlake/bootblock/report_platform.c:

https://review.coreboot.org/c/coreboot/+/62772/comment/9b8fc0c8_1711651d 
PS9, Line 16: #define PCI_DID_INTEL_NO_GT 0xffff
Remove? It's unused.

File src/soc/intel/meteorlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/62772/comment/5e76aeaf_8c2fd777 
PS13, Line 63: 
             : #define IOE_PCR_ABOVE_4G_BASE_ADDR	0x3fff0000000
             : #define IOE_P2SB_BAR		IOE_PCR_ABOVE_4G_BASE_ADDR
             : #define IOE_P2SB_SIZE		(256 * MiB)
             : 
             : #define IOM_BASE_ADDR		0x3fff0aa0000
             : #define IOM_BASE_SIZE		0x1600
             : #define IOM_BASE_ADDR_MAX	0x3fff0aa15ff
> Done

But these ranges are above 4 GiB, how can coreboot access them?