[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Lock down PCI BUSx:00.0 registers

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47448 )

Change subject: soc/intel/xeon_sp: Lock down PCI BUSx:00.0 registers
......................................................................

soc/intel/xeon_sp: Lock down PCI BUSx:00.0 registers

This is required for CbNT.

Change-Id: If5637eb8dd7de406b24b92100b68c5fa11c16854
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/uncore.c
3 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47448/1

diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 39ee8b4..62c7548 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -132,6 +132,10 @@
 #define PC10_IOAPIC_ID                  0x13
 #define PC11_IOAPIC_ID                  0x14

+// DMI3 B0D0F0 registers
+#define DMIRCBAR		0x50
+#define ERRINJCON		0x1d8
+
 // D7F7 registers
 #define IIO_DFX_LCK_CTL		0x504

diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 8455378..d26c894 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -176,6 +176,10 @@
 #define PC10_IOAPIC_ID                  0x13
 #define PC11_IOAPIC_ID                  0x14

+// DMI3 B0D0F0 registers
+#define DMIRCBAR		0x50
+#define ERRINJCON		0x1d8
+
 // D7F7 registers
 #define IIO_DFX_LCK_CTL		0x504

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index b01301c..7462ae5 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -356,6 +356,31 @@
    .device  = MMAP_VTD_STACK_CFG_REG_DEVID,
 };

+static void dmi3_init(struct device *dev)
+{
+	uint16_t pci_err_inj_dis = pci_read_config16(dev, ERRINJCON);
+	if (!(pci_err_inj_dis & 1))
+		pci_update_config16(dev, ERRINJCON, 0xfe, 1);
+
+	uint32_t dmircbar = pci_read_config32(dev, DMIRCBAR);
+	if (!(dmircbar & 1))
+		pci_update_config32(dev, DMIRCBAR, 0xfffe, 1);
+}
+
+static struct device_operations dmi3_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= dmi3_init,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver dmi3_driver __pci_driver = {
+	.ops		= &dmi3_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.device		= 0x2020,
+};
+
 static void d7_f7_init(struct device *dev)
 {
    uint16_t reg16;