[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86068?usp=email )

Change subject: soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param
......................................................................

soc/intel/elkhartlake/fsp_params.c: Adjust PchLegacyIoLowLatency param

According to Intel's recommendation for Time Coordinated Computing (TCC)
the FSP-S parameter PchLegacyIoLowLatency should be set to 'Enabled'
in order to promote low latencies on the PCH.
With the previous setting 'Disabled' low latencies on the PCH for
I/O operations are not enhanced.

Change-Id: I009cc10fee1f2cf2e2d7e6329cf98d2f95ea77b5
Signed-off-by: Johannes Hahn 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86068
Reviewed-by: Mario Scheithauer 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/elkhartlake/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Mario Scheithauer: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index 7b715f8..2f2e740 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -329,7 +329,7 @@
    	params->PsfTccEnable = 1;
    	params->PmcLpmS0ixSubStateEnableMask = 0;
    	params->PchDmiAspmCtrl = 0;
-		params->PchLegacyIoLowLatency = 0;
+		params->PchLegacyIoLowLatency = 1;
    	params->EnableItbm = 0;
    	params->D3ColdEnable = 0;
    	params->PmcOsIdleEnable = 0;