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Change subject: Revert "mb/google/brya/anahera: Disable autonomous GPIO power management" ......................................................................
Revert "mb/google/brya/anahera: Disable autonomous GPIO power management"
This reverts commit 550bdc9050eb97d1c4ddc8d6890cd1713d65ca89.
Reason for revert: <It breaks S0ix>
Change-Id: I24aa5578aed35319b3613595433329e6aed31fe1 --- M src/mainboard/google/brya/variants/anahera/overridetree.cb 1 file changed, 0 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/58810/1
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb index 7d003b3..0225f6c 100644 --- a/src/mainboard/google/brya/variants/anahera/overridetree.cb +++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb @@ -22,17 +22,6 @@ end end chip soc/intel/alderlake - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses; need to clarify - # the minimum PCH IRQ pulse width with Intel, b/180111628 - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |