Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52869 )
Change subject: vc/amd/fsp/cezanne: Add support for AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID ......................................................................
vc/amd/fsp/cezanne: Add support for AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID
This HOB describes the PCI routing table. It will be consumed by coreboot to generate the _PRT ACPI object.
BUG=b:184766519, b:184766197 TEST=Dump guybrush ACPI table and verify it looks correct.
Cq-Depend: chrome-internal:3794981 Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: Ib790004b88dfaf7671534f657c7735f6718114db --- M src/vendorcode/amd/fsp/cezanne/FspGuids.h A src/vendorcode/amd/fsp/cezanne/pcie_routing_hob.h 2 files changed, 84 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/52869/1
diff --git a/src/vendorcode/amd/fsp/cezanne/FspGuids.h b/src/vendorcode/amd/fsp/cezanne/FspGuids.h index 7f7a91d..c26ee24 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspGuids.h +++ b/src/vendorcode/amd/fsp/cezanne/FspGuids.h @@ -13,4 +13,8 @@ GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \ 0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8)
+#define AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID \ + GUID_INIT(0x00D54AA7, 0x0002, 0x47F5, \ + 0x00, 0x78, 0x08, 0x57, 0x00, 0x00, 0xA4, 0x11) + #endif /* __FSP_GUIDS__ */ diff --git a/src/vendorcode/amd/fsp/cezanne/pcie_routing_hob.h b/src/vendorcode/amd/fsp/cezanne/pcie_routing_hob.h new file mode 100644 index 0000000..87e5674 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/pcie_routing_hob.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _VC_AMD_FSP_PCIE_ROUTING_HOB_H_ +#define _VC_AMD_FSP_PCIE_ROUTING_HOB_H_ + +#include <console/console.h> +#include <fsp/util.h> +#include <FspGuids.h> +#include <types.h> + +/** + * Each PCI bridge has its INTx lines routed to one of the GNB IOAPIC PCI + * groups. Each group has 4 interrupts. The INTx lines can be swizzled before + * being routed to the IOAPIC. If the IOAPIC redirection entry is masked, the + * interrupt is reduced modulo 8 onto INT[A-H] and forwarded to the FCH IOAPIC. + **/ +struct pcie_routing_info { + uint8_t devfn; + uint8_t group; + uint8_t swizzle; + uint8_t irq; +}; + +enum pcie_swizzle_pin { + PIN_A, + PIN_B, + PIN_C, + PIN_D, +}; + +static const uint8_t pcie_swizzle_table[][4] = { + {PIN_A, PIN_B, PIN_C, PIN_D}, + {PIN_B, PIN_C, PIN_D, PIN_A}, + {PIN_C, PIN_D, PIN_A, PIN_B}, + {PIN_D, PIN_A, PIN_B, PIN_C}, +}; + +static inline const struct pcie_routing_info *get_pcie_routing_info(unsigned int devfn) +{ + const struct pcie_routing_info *routing_info; + size_t hob_size = 0, entries = 0; + + routing_info = fsp_find_extension_hob_by_guid(AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.b, + &hob_size); + + if (routing_info == NULL || hob_size == 0) { + printk(BIOS_ERR, "Couldn't find PCIe routing HOB.\n"); + return NULL; + } + + entries = hob_size / sizeof(*routing_info); + + for (size_t i = 0; i < entries; ++i, ++routing_info) + if (routing_info->devfn == devfn) + return routing_info; + + printk(BIOS_ERR, "Failed to find PCIe routing info for dev: %#x, fn: %#x\n", + PCI_SLOT(devfn), PCI_FUNC(devfn)); + + return NULL; +} + +static inline unsigned int pcie_calculate_irq(const struct pcie_routing_info *routing_info, + unsigned int pin) +{ + unsigned int irq; + + if (routing_info->swizzle > ARRAY_SIZE(pcie_swizzle_table)) + die("%s: swizzle %u out of bounds\n", __func__, routing_info->swizzle); + + if (pin > ARRAY_SIZE(pcie_swizzle_table[routing_info->swizzle])) + die("%s: pin %u out of bounds\n", __func__, pin); + + irq = routing_info->group * 4; + irq += pcie_swizzle_table[routing_info->swizzle][pin]; + + return irq; +} + +#endif /* _VC_AMD_FSP_PCIE_ROUTING_HOB_H_ */