[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: split southbridge into bootblock and ramstage code

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48439 )

Change subject: soc/amd/picasso: split southbridge into bootblock and ramstage code
......................................................................

soc/amd/picasso: split southbridge into bootblock and ramstage code

The ramstage parts gets renamed to fch.c and the bootblock one to
early_fch.c. No functionality from the old southbridge file is used in
romstage, so don't link it there.

Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/picasso/Makefile.inc
A src/soc/amd/picasso/early_fch.c
R src/soc/amd/picasso/fch.c
3 files changed, 61 insertions(+), 55 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 9c3720b..6e1d88b 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -13,7 +13,7 @@

bootblock-y += bootblock.c
 bootblock-y += aoac.c
-bootblock-y += southbridge.c
+bootblock-y += early_fch.c
 bootblock-y += i2c.c
 bootblock-y += uart.c
 bootblock-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
@@ -28,7 +28,6 @@
 romstage-y += uart.c
 romstage-$(CONFIG_PICASSO_CONSOLE_UART) += uart_console.c
 romstage-y += aoac.c
-romstage-y += southbridge.c
 romstage-y += psp.c
 romstage-y += mrc_cache.c

@@ -49,7 +48,7 @@
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c
 ramstage-y += gpio.c
 ramstage-y += aoac.c
-ramstage-y += southbridge.c
+ramstage-y += fch.c
 ramstage-y += reset.c
 ramstage-y += acp.c
 ramstage-y += sata.c
diff --git a/src/soc/amd/picasso/early_fch.c b/src/soc/amd/picasso/early_fch.c
new file mode 100644
index 0000000..f56a758
--- /dev/null
+++ b/src/soc/amd/picasso/early_fch.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpimmio.h>
+#include <amdblocks/espi.h>
+#include <amdblocks/lpc.h>
+#include <amdblocks/smbus.h>
+#include <amdblocks/spi.h>
+#include <console/console.h>
+#include <soc/i2c.h>
+#include <soc/southbridge.h>
+#include <soc/uart.h>
+#include <types.h>
+
+static void lpc_configure_decodes(void)
+{
+	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
+		lpc_enable_port80();
+}
+
+/* Before console init */
+void fch_pre_init(void)
+{
+	lpc_early_init();
+
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		lpc_configure_decodes();
+
+	fch_spi_early_init();
+	enable_acpimmio_decode_pm04();
+	fch_smbus_init();
+	fch_enable_cf9_io();
+	fch_enable_legacy_io();
+	enable_aoac_devices();
+	sb_reset_i2c_slaves();
+
+	/*
+	 * On reset Range_0 defaults to enabled. We want to start with a clean
+	 * slate to not have things unexpectedly enabled.
+	 */
+	clear_uart_legacy_config();
+
+	if (CONFIG(PICASSO_CONSOLE_UART))
+		set_uart_config(CONFIG_UART_FOR_CONSOLE);
+}
+
+/* After console init */
+void fch_early_init(void)
+{
+	fch_print_pmxc0_status();
+	i2c_soc_early_init();
+
+	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
+		lpc_disable_spi_rom_sharing();
+
+	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
+		espi_setup();
+		espi_configure_decodes();
+	}
+}
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/fch.c
similarity index 86%
rename from src/soc/amd/picasso/southbridge.c
rename to src/soc/amd/picasso/fch.c
index 03c424e..895a379 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/fch.c
@@ -14,18 +14,13 @@
 #include <amdblocks/amd_pci_util.h>
 #include <amdblocks/reset.h>
 #include <amdblocks/acpimmio.h>
-#include <amdblocks/espi.h>
-#include <amdblocks/lpc.h>
 #include <amdblocks/acpi.h>
-#include <amdblocks/smbus.h>
-#include <amdblocks/spi.h>
 #include <amdblocks/smi.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/i2c.h>
 #include <soc/southbridge.h>
 #include <soc/smi.h>
-#include <soc/uart.h>
 #include <soc/amd_pci_int_defs.h>
 #include <soc/pci_devs.h>
 #include <soc/nvs.h>
@@ -100,53 +95,6 @@
    misc_write32(MISC_CLK_CNTL1, ctrl);
 }

-static void lpc_configure_decodes(void)
-{
-	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
-		lpc_enable_port80();
-}
-
-/* Before console init */
-void fch_pre_init(void)
-{
-	lpc_early_init();
-
-	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
-		lpc_configure_decodes();
-
-	fch_spi_early_init();
-	enable_acpimmio_decode_pm04();
-	fch_smbus_init();
-	fch_enable_cf9_io();
-	fch_enable_legacy_io();
-	enable_aoac_devices();
-	sb_reset_i2c_slaves();
-
-	/*
-	 * On reset Range_0 defaults to enabled. We want to start with a clean
-	 * slate to not have things unexpectedly enabled.
-	 */
-	clear_uart_legacy_config();
-
-	if (CONFIG(PICASSO_CONSOLE_UART))
-		set_uart_config(CONFIG_UART_FOR_CONSOLE);
-}
-
-/* After console init */
-void fch_early_init(void)
-{
-	fch_print_pmxc0_status();
-	i2c_soc_early_init();
-
-	if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
-		lpc_disable_spi_rom_sharing();
-
-	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
-		espi_setup();
-		espi_configure_decodes();
-	}
-}
-
 void sb_enable(struct device *dev)
 {
    printk(BIOS_DEBUG, "%s\n", __func__);