Matt DeVillier (matt.devillier@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6024
-gerrit
commit 4b5c49b2df02f7ec2d3152507b153b3ea77f7afe Author: Matt DeVillier matt.devillier@gmail.com Date: Thu Jun 12 12:21:07 2014 -0500
panther: upstream config adjustments (3)
Replace calls to board-specific superIO methods with calls to common SIO methods; add defines needed for new SIO calls; update struct formatting to match other upstream boards
Change-Id: I51c72252800be64b9420d845e330fc0481c66470 Signed-off-by: Matt DeVillier matt.devillier@gmail.com --- src/mainboard/google/panther/romstage.c | 60 ++++++++++++++++++--------------- 1 file changed, 32 insertions(+), 28 deletions(-)
diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index 0f39b3b..c367968 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -31,6 +31,11 @@ #include "gpio.h" #include "superio/ite/it8772f/it8772f.h" #include "superio/ite/it8772f/early_serial.c" +#include "superio/ite/common/ite.h" + +#define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +
const struct rcba_config_instruction rcba_config[] = {
@@ -75,35 +80,35 @@ const struct rcba_config_instruction rcba_config[] = { void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: DEFAULT_PCIEXBAR, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: HPET_ADDR, - rcba: DEFAULT_RCBA, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - temp_mmio_base: 0xfed08000, - system_type: 5, /* ULT */ - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, - ec_present: 0, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, + .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, // Enable 2x refresh mode - ddr_refresh_2x: 1, - dq_pins_interleaved: 1, - max_ddr3_freq: 1600, - usb_xhci_on_resume: 1, - usb2_ports: { + .ddr_refresh_2x = 1, + .dq_pins_interleaved = 1, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ USB_PORT_MINI_PCIE }, @@ -122,7 +127,7 @@ void mainboard_romstage_entry(unsigned long bist) { 0x0000, 0, 0, /* P7: N/C */ USB_PORT_SKIP }, }, - usb3_ports: { + .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; CN22 */ { 1, 1 }, /* P2; CN23 */ @@ -139,11 +144,10 @@ void mainboard_romstage_entry(unsigned long bist) };
/* Early SuperIO setup */ - it8772f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); it8772f_ac_resume_southbridge(); pch_enable_lpc(); - it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1), - CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params);