Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31059 )
Change subject: src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller ......................................................................
Patch Set 9: Code-Review+1
(1 comment)
The clock stuff looks fine, but I'm unsure whether the PHY reset is required
https://review.coreboot.org/#/c/31059/9/src/mainboard/sifive/hifive-unleashe... File src/mainboard/sifive/hifive-unleashed/romstage.c:
https://review.coreboot.org/#/c/31059/9/src/mainboard/sifive/hifive-unleashe... PS9, Line 70: nsleep(2000000); : __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); : __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_EN), PHY_NRESET); : nsleep(100); : __sync_fetch_and_and(&GPIO_REG(GPIO_OUTPUT_VAL), ~PHY_NRESET); : nsleep(100); : __sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET); : nsleep(15000000); : } Is it necessary to do the PHY reset in coreboot, at all? I think Linux (or other OSes) should be able to reset the PHY.