The clock stuff looks fine, but I'm unsure whether the PHY reset is required
Patch set 9:Code-Review +1
1 comment:
File src/mainboard/sifive/hifive-unleashed/romstage.c:
nsleep(2000000);
__sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET);
__sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_EN), PHY_NRESET);
nsleep(100);
__sync_fetch_and_and(&GPIO_REG(GPIO_OUTPUT_VAL), ~PHY_NRESET);
nsleep(100);
__sync_fetch_and_or(&GPIO_REG(GPIO_OUTPUT_VAL), PHY_NRESET);
nsleep(15000000);
}
Is it necessary to do the PHY reset in coreboot, at all?
I think Linux (or other OSes) should be able to reset the PHY.
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