[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Fix memory corruptions

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46504 )

Change subject: soc/intel/cannonlake: Fix memory corruptions
......................................................................

soc/intel/cannonlake: Fix memory corruptions

Coverity detects source memory is overrun. Fix this issue by using
the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption.

Found-by: Coverity CID 1429762 1429774
TEST=None

Signed-off-by: John Zhao 
Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index d66e890a..fe7641f 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -355,14 +355,14 @@

memcpy(params->PcieRpAdvancedErrorReporting,
    	config->PcieRpAdvancedErrorReporting,
-		sizeof(params->PcieRpAdvancedErrorReporting));
+		sizeof(config->PcieRpAdvancedErrorReporting));

memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
           sizeof(config->PcieRpLtrEnable));
    memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
           sizeof(config->PcieRpSlotImplemented));
    memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
-	       sizeof(params->PcieRpHotPlug));
+	       sizeof(config->PcieRpHotPlug));

for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
    	params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];