[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58983 )

Change subject: soc/amd/cezanne/romstage: Call preload_ramstage
......................................................................

soc/amd/cezanne/romstage: Call preload_ramstage

This will use the SPI DMA controller to preload ramstage while FSP-M
executes.

BUG=b:179699789
TEST=Boot nipperkin to OS and see 12ms reduction in boot time.
| 8 - starting to load ramstage                       | 0         | 0.001     Δ(  0.00,    0.00%) |
| 15 - starting LZMA decompress (ignore for x86)      | 0.003     | 0.027     Δ(  0.02,    0.00%) |
| 16 - finished LZMA decompress (ignore for x86)      | 26.475    | 14.486    Δ(-11.99,   -0.78%) |
| 9 - finished loading ramstage                       | 0.548     | 0.559     Δ(  0.01,    0.00%) |

We can achieve even more speed savings by having FSP-M call
thread_yield() so we can preload more than 64KiB. Once we do that we
can also switch the compression algorithm to LZ4 which will make the
decompression time ~1ms.

Signed-off-by: Raul E Rangel 
Change-Id: I93ae358986059cdae6069421f4efba586235df51
---
M src/soc/amd/cezanne/fsp_m_params.c
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/58983/1

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 9f594d9..a220ab0 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -7,6 +7,7 @@
 #include <console/uart.h>
 #include <device/device.h>
 #include <fsp/api.h>
+#include <program_loading.h>
 #include <soc/platform_descriptors.h>
 #include <soc/pci_devs.h>
 #include <string.h>
@@ -160,4 +161,16 @@
    fsp_fill_pcie_ddi_descriptors(mcfg);
    fsp_assign_ioapic_upds(mcfg);
    mb_pre_fspm();
+
+	/*
+	 * At this point FSP-M has been loaded into RAM. If we were to start preloading before
+	 * FSP-M was loaded, we would introduce contention onto the SPI bus and
+	 * slow down the FSP-M read from SPI. Since FSP-M takes a while to execute and performs
+	 * no SPI operations, we can preload while FSP-M executes.
+	 *
+	 * While FSP-M is executing, it's not currently possible to enqueue other transactions
+	 * because FSP-M doesn't call `thread_yield()`. So the other preloads will start loading
+	 * right after FSP-M completes.
+	 */
+	preload_ramstage();
 }