[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: correct USB2 phy parameter naming problem

[Kevin Chiu (Code Review)]

Hello Kevin Chiu,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/47734

to review the following change.

Change subject: soc/amd/picasso: correct USB2 phy parameter naming problem
......................................................................

soc/amd/picasso: correct USB2 phy parameter naming problem

From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune

BUG=None
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kevin Chiu 
Change-Id: I50af0d28eeb89aaca20b0d89d8a9890564d538fc
---
M src/soc/amd/picasso/chip.h
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47734/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 9d8fb8e..28d2040 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -30,7 +30,7 @@
    /* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
    uint8_t	tx_rise_tune;
    /* HS DC Voltage Level Adjustment. Range 0 - 0xF */
-	uint8_t	rx_vref_tune;
+	uint8_t	tx_vref_tune;
    /* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
    uint8_t	tx_hsxv_tune;
    /* USB Source Impedance Adjustment. Range 0 - 0x3. */