Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63460 )
Change subject: soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S ......................................................................
soc/intel/alderlake/Kconfig: Set correct P2SB BAR for ADL PCH-S
According to Intel DOC #630603 P2SB BAR must be at 0xe0000000 for PCH-S.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: Ie6db3f7108ff1edf62c94876412adfc6421034d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63460 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b631624..35fd2f7 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -251,6 +251,7 @@
config PCR_BASE_ADDRESS hex + default 0xe0000000 if SOC_INTEL_ALDERLAKE_PCH_S default 0xfd000000 help This option allows you to select MMIO Base Address of sideband bus.
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.