Attention is currently required from: Furquan Shaikh. Neill Corlett has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50101 )
Change subject: hatch: Modify genesis PcieClkSrc settings ......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50101/comment/1af6d09d_cff95bd4 PS1, Line 7: Modify genesis PcieClkSrc settings to work around issue with Longsys SSD, per recommendations from Quanta.
Commit message guidelines: https://www.coreboot. […]
Updated word wrapping; please let me know if I need to remove the CrOS-specific metadata as well
File src/mainboard/google/hatch/variants/genesis/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/50101/comment/711eb6b4_40a1ee20 PS1, Line 217: #register "PcieClkSrcUsage[1]" = "10" : #register "PcieClkSrcClkReq[1]" = "1"
Is there an external clock being used? The comment on line 216 isn't correct anymore. […]
Presumably there's an external clock. I'm relaying this patch from Quanta, who were able to get a Longsys SSD working on the NVMe port with this change plus another change to ME firmware. I've dropped the lines and the inaccurate comment.