Hello Martin Roth, Furquan Shaikh,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/34420
to review the following change.
Change subject: _WIP_ soc/amd/picasso: Update for USB3.1 ......................................................................
_WIP_ soc/amd/picasso: Update for USB3.1
todo: still need OC support b:130280788
Change to the appropriate device IDs. Remove the ehci resource call.
Remove unused USB2 ACPI name assignment.
Change-Id: Ic287a05b30ca03e3371cc4a30aaa93b236c6d3fb Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com --- M src/soc/amd/picasso/chip.c M src/soc/amd/picasso/usb.c 2 files changed, 3 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34420/1
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 65d98b1..8d49271 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -49,19 +49,6 @@ case 0: /* Root Hub */ return "RHUB"; - case 2: - /* USB2 ports */ - switch (dev->path.usb.port_id) { - case 0: return "HS01"; - case 1: return "HS02"; - case 2: return "HS03"; - case 3: return "HS04"; - case 4: return "HS05"; - case 5: return "HS06"; - case 6: return "HS07"; - case 7: return "HS08"; - } - break; case 3: /* USB3 ports */ switch (dev->path.usb.port_id) { diff --git a/src/soc/amd/picasso/usb.c b/src/soc/amd/picasso/usb.c index 66c8266..7d3201c 100644 --- a/src/soc/amd/picasso/usb.c +++ b/src/soc/amd/picasso/usb.c @@ -56,7 +56,7 @@ };
static struct device_operations usb_ops = { - .read_resources = pci_ehci_read_resources, + .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = set_usb_over_current, @@ -66,12 +66,8 @@ };
static const unsigned short pci_device_ids[] = { - PCI_DEVICE_ID_AMD_SB900_USB_18_0, - PCI_DEVICE_ID_AMD_SB900_USB_18_2, - PCI_DEVICE_ID_AMD_SB900_USB_20_5, - PCI_DEVICE_ID_AMD_CZ_USB_0, - PCI_DEVICE_ID_AMD_CZ_USB_1, - PCI_DEVICE_ID_AMD_CZ_USB3_0, + PCI_DEVICE_ID_AMD_PCO_XHCI0, + PCI_DEVICE_ID_AMD_PCO_XHCI1, 0 };