Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5472
-gerrit
commit 6c71bcf02e929b70c992ee084cbb452c9a1a23f2 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon Apr 7 14:59:42 2014 +1000
jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()
Follow same reasoning as: 12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio() Use coreboot variants for PCI and MSR access over AGESA's.
Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 59 ++++++++++-------------- src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 2 +- 2 files changed, 25 insertions(+), 36 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c index e6633f3..1627f25 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c @@ -26,9 +26,12 @@ #include "BiosCallOuts.h" #include "PlatformGnbPcieComplex.h"
+#define __SIMPLE_DEVICE__ + #include <arch/acpi.h> #include <arch/io.h> #include <cbmem.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <stdint.h> #include <string.h> @@ -74,53 +77,39 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *------------------------------------------------------------------------------ */ -UINT32 -agesawrapper_amdinitcpuio ( - VOID - ) +uint32_t agesawrapper_amdinitcpuio(void) { - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; + pci_devfn_t dev; + msr_t msr; + uint32_t reg32; + + dev = PCI_DEV(0, 0x18, 1);
/* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0xf4, 1);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * set to non-posted regions. + * Last address before processor local APIC at FEE00000 */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; // last address before processor local APIC at FEE00000 - PciData |= 1 << 7; // set NP (non-posted) bit - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; // lowest NP address is HPET at FED00000 - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); + + /* Lowest NP address is HPET at FED00000 */ + pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3);
/* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; // last address before non-posted range - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + pci_io_write_config32(dev, 0x8C, 0x00fecf00); + + msr = rdmsr(0xc001001a); + reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ + pci_io_write_config32(dev, 0x88, reg32);
/* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return (UINT32)Status; + pci_io_write_config32(dev, 0xc4, 0x0000f000); + pci_io_write_config32(dev, 0xc0, 0x00000003); + + return AGESA_SUCCESS; }
UINT32 diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h index 6544d25..6af5e5f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h +++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h @@ -82,7 +82,7 @@ UINT32 agesawrapper_amdinitmid (void);
UINT32 agesawrapper_amdreadeventlog (void);
-UINT32 agesawrapper_amdinitcpuio (void); +uint32_t agesawrapper_amdinitcpuio (void); UINT32 agesawrapper_amdinitmmio (void); UINT32 agesawrapper_amdinitresume (void); UINT32 agesawrapper_amdS3Save (void);