[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure RP setting

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40262 )

Change subject: soc/intel/tigerlake: Configure RP setting
......................................................................

soc/intel/tigerlake: Configure RP setting

Add LTR and AER configuration to the root ports config.

BUG=b:151166040
TEST= build and boot volteer and check LTR and AER value
from FSP log

Signed-off-by: Wonkyu Kim 
Change-Id: I668f2e5fea15019a9e5ae06fb4d55fa2aea69e8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40262
Reviewed-by: Srinidhi N Kaushik 
Reviewed-by: Nick Vaccaro 
Reviewed-by: Paul Menzel 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 11 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Nick Vaccaro: Looks good to me, but someone else must approve
  Srinidhi N Kaushik: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index e105061..bc6c3db 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -118,6 +118,12 @@
    	L1_SS_L1_2,
    } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS];

+	/* PCIe LTR: Enable (1) / Disable (0) */
+	uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
+
+	/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
+	uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
+
    /* SMBus */
    uint8_t SmbusEnable;

diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index ff6d3a9..231399c 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -122,10 +122,13 @@
    }

/* RP Configs */
-	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++)
+	for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) {
    	params->PcieRpL1Substates[i] =
    		get_l1_substate_control(config->PcieRpL1Substates[i]);
-
+		params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i];
+		params->PcieRpAdvancedErrorReporting[i] =
+			config->PcieRpAdvancedErrorReporting[i];
+	}
    /* Enable xDCI controller if enabled in devicetree and allowed */
    dev = pcidev_on_root(PCH_DEV_SLOT_XHCI, 1);
    if (dev) {