Change subject: soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
......................................................................
Sounds good. I'll be happy to review. Some exceptions to account for: […]
--
To view, visit
https://review.coreboot.org/c/coreboot/+/45759
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Gerrit-Change-Number: 45759
Gerrit-PatchSet: 6
Gerrit-Owner: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: Angel Pons
th3fanbus@gmail.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Martin Roth
martinroth@google.com
Gerrit-Reviewer: Patrick Georgi
pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: HAOUAS Elyes
ehaouas@noos.fr
Gerrit-Comment-Date: Tue, 29 Sep 2020 10:39:55 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Angel Pons
th3fanbus@gmail.com
Comment-In-Reply-To: Subrata Banik
subrata.banik@intel.com
Gerrit-MessageType: comment