[coreboot-gerrit] Change in ...coreboot[master]: riscv: create Kconfig architecture features for new parts

[ron minnich (Code Review)]

ron minnich has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30348 )

Change subject: riscv: create Kconfig architecture features for new parts
......................................................................

riscv: create Kconfig architecture features for new parts

RISCV parts can be created with any one of four CPU modes enabled,
with or without PMP, and with either 32 or 64 bit XLEN.

In anticipation of parts to come, create the Kconfig variables for these
architecture attributes.

Change-Id: I32ee51b2a469c7684a2f1b477bdac040e972e253
Signed-off-by: Ronald G. Minnich 
Reviewed-on: https://review.coreboot.org/c/30348
Reviewed-by: Patrick Georgi 
Reviewed-by: Stefan Reinauer 
Tested-by: build bot (Jenkins) 
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
M src/soc/sifive/fu540/Kconfig
M src/soc/ucb/riscv/Kconfig
4 files changed, 61 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Stefan Reinauer: Looks good to me, approved

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index 9fa43bc..5bde804 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -11,6 +11,44 @@
 config RISCV_CODEMODEL
    string

+config ARCH_RISCV_M_DISABLED
+	bool
+
+config ARCH_RISCV_M
+	# Whether a SOC implements M mode.
+	# M mode is the most privileged mode, it is
+	# the equivalent in some ways of x86 SMM mode
+	# save that in M mode it is impossible to turn
+	# on paging.
+	# While the spec requires it, there is at least
+	# one implementation that will not have it due
+	# to security concerns.
+	bool
+	default n if ARCH_RISCV_M_DISABLED
+	default y
+
+config ARCH_RISCV_S
+	# S (supervisor) mode is for kernels. It is optional.
+	bool
+	default n
+
+config ARCH_RISCV_U
+	# U (user) mode is for programs.
+	bool
+	default n
+
+config ARCH_RISCV_RV64
+	bool
+	default n
+
+config ARCH_RISCV_RV32
+	bool
+	default n
+
+config ARCH_RISCV_PMP
+	bool
+	default n
+
 config ARCH_BOOTBLOCK_RISCV
    bool
    default n
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index aee4b3b..e4c8468 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -26,10 +26,21 @@
 endif

riscv_flags = -I$(src)/arch/riscv/
+
+ifeq ($(CONFIG_ARCH_RISCV_RV64),y)
+_rv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64
+else
+ifeq ($(CONFIG_ARCH_RISCV_RV32),y)
+_rv_flags += -D__riscv -D__riscv_xlen=32 -D__riscv_flen=32
+else
+$(error "You need to select ARCH_RISCV_RV64 or ARCH_RISCV_RV32")
+endif
+endif
+
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 riscv_flags += -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI) -mcmodel=$(CONFIG_RISCV_CODEMODEL)
 else
-riscv_flags += -D__riscv -D__riscv_xlen=64 -D__riscv_flen=64
+riscv_flags += $(_rv_flags)
 endif

riscv_asm_flags = -march=$(CONFIG_RISCV_ARCH) -mabi=$(CONFIG_RISCV_ABI)
@@ -56,7 +67,7 @@
 bootblock-y += boot.c
 bootblock-y += smp.c
 bootblock-y += misc.c
-bootblock-y += pmp.c
+bootblock-$(ARCH_RISCV_PMP) += pmp.c
 bootblock-y += \
    $(top)/src/lib/memchr.c \
    $(top)/src/lib/memcmp.c \
@@ -85,7 +96,7 @@
 romstage-y += boot.c
 romstage-y += stages.c
 romstage-y += misc.c
-romstage-y += pmp.c
+romstage-$(ARCH_RISCV_PMP) += pmp.c
 romstage-y += smp.c
 romstage-y += \
    $(top)/src/lib/memchr.c \
@@ -127,7 +138,7 @@
 ramstage-y += boot.c
 ramstage-y += tables.c
 ramstage-y += payload.S
-ramstage-y += pmp.c
+ramstage-$(ARCH_RISCV_PMP) += pmp.c
 ramstage-y += \
    $(top)/src/lib/memchr.c \
    $(top)/src/lib/memcmp.c \
diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig
index 25b4b46..7910b37 100644
--- a/src/soc/sifive/fu540/Kconfig
+++ b/src/soc/sifive/fu540/Kconfig
@@ -14,6 +14,10 @@
 config SOC_SIFIVE_FU540
    bool
    select ARCH_RISCV
+	select ARCH_RISCV_RV64
+	select ARCH_RISCV_S
+	select ARCH_RISCV_U
+	select ARCH_RISCV_PMP
    select ARCH_BOOTBLOCK_RISCV
    select ARCH_VERSTAGE_RISCV
    select ARCH_ROMSTAGE_RISCV
diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index 638d734..5a43aa6 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -1,5 +1,9 @@
 config SOC_UCB_RISCV
    select ARCH_RISCV
+	select ARCH_RISCV_RV64
+	select ARCH_RISCV_S
+	select ARCH_RISCV_U
+	select ARCH_RISCV_PMP
    select ARCH_BOOTBLOCK_RISCV
    select ARCH_VERSTAGE_RISCV
    select ARCH_ROMSTAGE_RISCV