[coreboot-gerrit] Change in coreboot[master]: [WIP] soc/intel/denverton: Handle MMCONF_BASE_ADDRESS

[Angel Pons (Code Review)]

Attention is currently required from: Mariusz Szafrański, Paul Menzel, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Kyösti Mälkki, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50665 )

Change subject: [WIP] soc/intel/denverton: Handle MMCONF_BASE_ADDRESS
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> It is hardcoded to 0xe0000000 and configured inside FSP-T TempRamInit call

How many busses does FSP-T enable?