Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35372 )
Change subject: intel/nehalem: Refactor ACPI S3 detection ......................................................................
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there are no boards that use elog on nehalem. I'd recommend to remove the whole elog code on this platform instead.
ELOG depends on BOOT_DEVICE_SUPPORTS_WRITES, so everything ELOG -related under southbridge/intel and northbridge/intel never builds. Looks like a regression from CB:16204?
Their spi flash controller needs to work early on in the bootflow (romstage). In the past nearly all intel spi flash controller implementations only worked in ramstage. But if that CL prevented ramstage elog as well it could certainly be seen as a regression. However, I'm not sure how many mainboards were using elog that leveraged those southbridge/intel and northbridge/intel pieces of code. lynxpoint and something else may have, but I'm not sure the order of operations of refactoring the code that may have busted stuff.
I think ELOG was always selected with CHROMEOS, but I did not check deeper into this.
Possibly affected: samsung/lumpy,stumpy (sandy / bd82x6x) google/butterfly,link,parrot,stout (ivy / c216) google/beltino,slippy (haswell / lynxpoint)