[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake: Introduce memmap.h

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45379 )

Change subject: nb/intel/ironlake: Introduce memmap.h
......................................................................

nb/intel/ironlake: Introduce memmap.h

Move all memory map definitions into a separate header.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I1f37ad9cae39041f98871c613b308b5ac5da01b3
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45379
Reviewed-by: Patrick Georgi 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/ironlake/ironlake.h
A src/northbridge/intel/ironlake/memmap.h
2 files changed, 18 insertions(+), 9 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Georgi: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 8abc3fc..382e080 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -5,11 +5,6 @@

#define DEFAULT_HECIBAR		((u8 *)0xfed17000)

-#define IOMMU_BASE1 0xfed90000
-#define IOMMU_BASE2 0xfed91000
-#define IOMMU_BASE3 0xfed92000
-#define IOMMU_BASE4 0xfed93000
-
 /*
  * D1:F0 PEG
  */
@@ -24,10 +19,7 @@
 #define IRONLAKE_DESKTOP	1
 #define IRONLAKE_SERVER		2

-/* Northbridge BARs */
-#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
-#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
-#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+#include "memmap.h"

#define QUICKPATH_BUS 0xff

@@ -87,6 +79,7 @@
 #define QPI_PHY_EP_SELECT	0xe0 /* QPI Phys. Layer Electrical Parameter Select */
 #define QPI_PHY_EP_MCTR		0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */

+
 /* Device 0:2.0 PCI configuration space (Graphics Device) */

#define MSAC		0x62	/* Multi Size Aperture Control */
diff --git a/src/northbridge/intel/ironlake/memmap.h b/src/northbridge/intel/ironlake/memmap.h
new file mode 100644
index 0000000..cd7708c
--- /dev/null
+++ b/src/northbridge/intel/ironlake/memmap.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__
+#define __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__
+
+/* Northbridge BARs */
+#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
+#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+
+#define IOMMU_BASE1		0xfed90000
+#define IOMMU_BASE2		0xfed91000
+#define IOMMU_BASE3		0xfed92000
+#define IOMMU_BASE4		0xfed93000
+
+#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_MEMMAP_H__ */