[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add DDR4 mem configuration

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39040 )

Change subject: soc/intel/tigerlake: add DDR4 mem configuration
......................................................................

Patch Set 6:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39040/6/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39040/6/src/soc/intel/tigerlake/inc... 
PS6, Line 65: Rcomp
This is not correct.

https://review.coreboot.org/c/coreboot/+/39040/4/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/meminit_tgl.h:

https://review.coreboot.org/c/coreboot/+/39040/4/src/soc/intel/tigerlake/inc... 
PS4, Line 75: spd_addr_table
> As far as I know this was the only option right now.

Wait. Are you saying that TGL FSP with DDR4 memory does not support passing in SPD data directly? i.e. setting of MemorySpdPtr* UPDs?