Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39098 )
Change subject: soc/intel/tigerlake: Integrate Legacy 8254 timer support ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... File src/soc/intel/tigerlake/fsp_params_tgl.c:
https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... PS2, Line 139: Enable8254ClockGating Looks like these are reserved in the stripped FSP headers, it will need to be added back for this to compile. (why was this particular UPD sanitized in the first place?)
https://review.coreboot.org/c/coreboot/+/39098/2/src/soc/intel/tigerlake/fsp... PS2, Line 140: 1 It looks like if Enable8254ClockGating==0 but ..OnS3==1 then it will end up setting the clock gating bit on resume (from ItssLib.c). Should these both depend on the config option?