build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/5/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/5/src/soc/intel/alderlake/rom... PS5, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i; space required before the open parenthesis '('
https://review.coreboot.org/c/coreboot/+/48340/5/src/soc/intel/alderlake/rom... PS5, Line 50: if(config->PcieRp[i].clkusage) ? config->PcieRp[i].clkusage : i; trailing statements should be on next line