[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Add provision to skip postcar and load ramstage

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34754 )

Change subject: soc/intel/cannonlake: Add provision to skip postcar and load ramstage
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soc/intel/cannonlake: Add provision to skip postcar and load ramstage

This patch adds required provision in soc code to pick ramstage
directly from romstage and avoid postcar as intermediate stage for
car tear down.

Change-Id: I6f1d93ae0f8d957bf9c15e358bc13039a300c4ca
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/romstage/romstage.c
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/34754/1

diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 94b9899..3aefb97 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -127,6 +127,23 @@
    printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
 }

+#if !CONFIG(HAVE_POSTCAR)
+/*
+ * Make sure we are enabling intermediate caching to speed up
+ * ramstage.elf loading and decompression as we are still in romstage
+ * and car tear down will be handled by ramstage at its entry.
+ */
+static void enable_ramstage_caching(uintptr_t base, size_t size)
+{
+	int mtrr = get_free_var_mtrr();
+
+	if (mtrr == -1)
+		return;
+
+	set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT);
+}
+#endif
+
 asmlinkage void car_stage_entry(void)
 {
    bool s3wake;
@@ -164,5 +181,10 @@
    /* Cache the ROM as WP just below 4GiB. */
    postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);

+#if CONFIG(HAVE_POSTCAR)
    run_postcar_phase(&pcf);
+#else
+	enable_ramstage_caching(top_of_ram, 16*MiB);
+	run_ramstage_phase(&pcf);
+#endif
 }