[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/common/psp: Check more error bits before SPL fusing

[Martin L Roth (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73518 )

Change subject: soc/amd/common/psp: Check more error bits before SPL fusing
......................................................................

soc/amd/common/psp: Check more error bits before SPL fusing

This adds checks for three more error bits before requesting that the
SPL fuses are updated.

- While I'm here, I'm adding the include of types.h which was previously
done through other include files, but should be done independently.

Signed-off-by: Martin Roth 
Change-Id: I87a7d40850c4e9ddbb2d1913c1588a919fdb29d2
---
M src/soc/amd/common/block/psp/psp_gen2.c
1 file changed, 37 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/73518/1

diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c
index f7ee5bb..f49b3d4 100644
--- a/src/soc/amd/common/block/psp/psp_gen2.c
+++ b/src/soc/amd/common/block/psp/psp_gen2.c
@@ -3,6 +3,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <timer.h>
+#include <types.h>
 #include <amdblocks/psp.h>
 #include <amdblocks/smn.h>
 #include "psp_def.h"
@@ -12,7 +13,10 @@
 #define PSP_MAILBOX_BUFFER_H_OFFSET	0x10578 /* 4 bytes */

#define CORE_2_PSP_MSG_38_OFFSET	0x10998 /* 4 byte */
-#define   CORE_2_PSP_MSG_38_FUSE_SPL	BIT(12)
+#define   CORE_2_PSP_MSG_38_FUSE_SPL		BIT(12)
+#define   CORE_2_PSP_MSG_38_SPL_FUSE_ERROR	BIT(13)
+#define   CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR	BIT(14)
+#define   CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING	BIT(15)

union pspv2_mbox_command {
    u32 val;
@@ -131,6 +135,22 @@
    	return;
    }

+	if (c2p38 & CORE_2_PSP_MSG_38_SPL_FUSE_ERROR) {
+		printk(BIOS_ERR, "PSP: SPL Table does not meet fuse requirements.\n");
+		return;
+	}
+
+	if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_ERROR) {
+		printk(BIOS_ERR, "PSP: Critical SPL entry missing or current firmware does"
+				   " not meet requirements.\n");
+		return;
+	}
+
+	if (c2p38 & CORE_2_PSP_MSG_38_SPL_ENTRY_MISSING) {
+		printk(BIOS_ERR, "PSP: Table of critical SPL values is missing.\n");
+		return;
+	}
+
    if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_FUSE_SPL))
    	return;