Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39669 )
Change subject: mb/intel/jasperlake_rvp: Add camera support Jasper Lake RVP ......................................................................
mb/intel/jasperlake_rvp: Add camera support Jasper Lake RVP
Add support as per the schmatics Add 2 Ports and 2 Endpoints Add support for OTVI5676
Signed-off-by: Pandya, Varshit B varshit.b.pandya@intel.com Change-Id: I07ae9e3473c16bde8eb1597460e70cc478357b98 --- M src/mainboard/intel/jasperlake_rvp/Kconfig M src/mainboard/intel/jasperlake_rvp/Kconfig.name M src/mainboard/intel/jasperlake_rvp/dsdt.asl A src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl A src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl A src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl A src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl A src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c A src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl 11 files changed, 611 insertions(+), 16 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/39669/1
diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig b/src/mainboard/intel/jasperlake_rvp/Kconfig index 97b038e..edf1bea 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig @@ -50,4 +50,10 @@ config UART_FOR_CONSOLE int default 2 + +config VARIANT_HAS_CAMERA_ACPI + bool + default n + help + Select this option to enable camera ACPI support on the variant endif diff --git a/src/mainboard/intel/jasperlake_rvp/Kconfig.name b/src/mainboard/intel/jasperlake_rvp/Kconfig.name index 1a56f05..d0fa41e 100644 --- a/src/mainboard/intel/jasperlake_rvp/Kconfig.name +++ b/src/mainboard/intel/jasperlake_rvp/Kconfig.name @@ -1,5 +1,6 @@ config BOARD_INTEL_JASPERLAKE_RVP bool "Jasperlake DDR4/LPDDR4 RVP" + select VARIANT_HAS_CAMERA_ACPI
config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC" diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl index c996717..81677df 100644 --- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl +++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl @@ -41,13 +41,15 @@ } }
-#if CONFIG(CHROMEOS) - /* Chrome OS specific */ - #include <vendorcode/google/chromeos/acpi/chromeos.asl> -#endif
-#if CONFIG(EC_GOOGLE_CHROMEEC) - /* Chrome OS Embedded Controller */ + + #if CONFIG(CHROMEOS) + /* Chrome OS specific */ + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + #endif + + #if CONFIG(EC_GOOGLE_CHROMEEC) + /* Chrome OS Embedded Controller */ Scope (_SB.PCI0.LPCB) { /* ACPI code for EC SuperIO functions */ @@ -55,7 +57,12 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } -#endif + #endif + + #if CONFIG(VARIANT_HAS_CAMERA_ACPI) + /* Camera */ + #include <variant/acpi/camera.asl> + #endif
#include <southbridge/intel/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl new file mode 100644 index 0000000..f560d4a --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam0.asl @@ -0,0 +1,168 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0.I2C4) +{ + PowerResource (RCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) // _ON_: Power On + { + If ((STA == Zero)) + { + // Enable CLK0 + MCCT(0,1,1) // Clock 0, enable, 19.2MHz + // Pull PWREN(GPIO D5) high + STXS(GPP_D5) + Sleep(5) + // Pull RST(GPIO B14) low + CTXS(GPP_B14) + Sleep(5) + // Pull RST high + STXS(GPP_B14) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) // _OFF: Power Off + { + If ((STA == One)) + { + // Pull RST low + CTXS(GPP_B14) + // Pull PWREN low + CTXS(GPP_D5) + // Disable CLK0 + MCCT(0,0,1) // Clock 0, disable, 19.2MHz + // STA = Zero + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM0) + { + Name (_HID, "OVTI5675") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 5675 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + RCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + RCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + }, + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + Zero, + Zero + } + } + } + }) + } + +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl new file mode 100644 index 0000000..9187ed6 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/cam1.asl @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0.I2C5) +{ + PowerResource (FCPR, 0x00, 0x0000) + { + Name (STA, Zero) + Method (_ON, 0, Serialized) // _ON_: Power On + { + If ((STA == Zero)) + { + // Enable CLK1 + MCCT(1,1,1) // Clock 1, enable, 19.2MHz + // Pull PWREN(GPIO R6) high + STXS(GPP_D4) + Sleep(5) + // Pull RST(GPIO H12) low + CTXS(GPP_C19) + Sleep(5) + // Pull RST high + STXS(GPP_C19) + Sleep(5) + Store(1,STA) + } + } + + Method (_OFF, 0, Serialized) // _OFF: Power Off + { + If ((STA == One)) + { + // Pull RST low + CTXS(GPP_C19) + // Pull PWREN low + CTXS(GPP_D4) + // Disable CLK0 + MCCT(1,0,1) // Clock 1, disable, 19.2MHz + Store(0,STA) + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (STA) + } + } + + Device (CAM1) + { + Name (_HID, "OVTI5675") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_DDN, "Ov 5675 Camera") // _DDN: DOS Device Name + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + I2cSerialBus (0x0036, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\_SB.PCI0.I2C5", + 0x00, ResourceConsumer, , + ) + }) + + Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 + { + FCPR + }) + + Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot + { + FCPR + }) + + Name (_DSD, Package (0x04) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "port0", + "PRT0" + } + }, + + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "clock-frequency", + 0x0124F800 + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x03) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "link-frequencies", + Package (0x01) + { + 0x325AA000 + } + }, + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + IPU0, + One, + Zero + } + } + } + }) + } +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl new file mode 100644 index 0000000..542a274 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/camera.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "ipu_mainboard.asl" +#include "ipu_endpoints.asl" +#include "cam0.asl" +#include "cam1.asl" diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl new file mode 100644 index 0000000..f684c6b --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_endpoints.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +cope (_SB.PCI0.IPU0) +{ + Name (EP00, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C4.CAM0, + Zero, + Zero + } + } + } + }) + Name (EP10, Package (0x02) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x04) + { + Package (0x02) + { + "endpoint", + Zero + }, + + Package (0x02) + { + "clock-lanes", + Zero + }, + + Package (0x02) + { + "data-lanes", + Package (0x02) + { + One, + 0x02, + } + }, + + Package (0x02) + { + "remote-endpoint", + Package (0x03) + { + ^I2C5.CAM1, + Zero, + Zero + } + } + } + }) +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl new file mode 100644 index 0000000..64bfc71 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/baseboard/include/baseboard/acpi/ipu_mainboard.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (_SB.PCI0) +{ + Device (IPU0) + { + Name (_ADR, 0x00050000) // _ADR: Address + Name (_DDN, "Camera and Imaging Subsystem") // _DDN: DOS Device Name + } +} + +Scope (_SB.PCI0.IPU0) +{ + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x02) + { + Package (0x02) + { + "port0", + "PRT0" + }, + + Package (0x02) + { + "port1", + "PRT1" + } + } + }) + + Name (PRT0, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + Zero + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP00" + } + } + }) + + Name (PRT1, Package (0x04) + { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package (0x01) + { + Package (0x02) + { + "port", + 2 + } + }, + + ToUUID ("dbb8e3e6-5886-4ba6-8795-1319f52a966b"), + Package (0x01) + { + Package (0x02) + { + "endpoint0", + "EP10" + } + } + }) +} diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 9c40f66..946b4be 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -73,7 +73,7 @@ [PchSerialIoIndexI2C1] = PchSerialIoPci, [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoPci, [PchSerialIoIndexI2C5] = PchSerialIoPci, }"
@@ -116,13 +116,20 @@ .speed_mhz = 1, .early_init = 1, }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, }"
device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device - device pci 12.0 off end # Thermal Subsystem + device pci 04.0 off end # SA Thermal device + device pci 05.0 on end #IPU + device pci 12.0 off end # Thermal Subsystem device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 14.0 on @@ -229,9 +236,9 @@ device i2c 2c on end end end # I2C 0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R @@ -240,7 +247,7 @@ device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 off end # SATA device pci 19.0 on end # I2C #4 - device pci 19.1 off end # I2C #5 + device pci 19.1 on end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC device pci 1c.0 off end # PCI Express Port 1 @@ -262,7 +269,7 @@ device spi 0 on end end end # GSPI #1 - device pci 1f.0 on end # eSPI Interface + device pci 1f.0 on end # eSPI Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index 91292b8..850a9b4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -18,7 +18,26 @@
/* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* B14 : CAM1_RST_N */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + + /* D4 : CAM2_PWREN */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : CRD_CAM_PWREN */ + PAD_CFG_GPO(GPP_D5, 0, PLTRST), + /* D12 : GPPC_D_12_I2C4B_SDA_CRD1 */ + PAD_CFG_NF(GPP_D12, NONE, PLTRST, NF3), + /* D13 : GPPC_D_13_I2C4B_SCL_CRD1 */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF3), + /* D22 : GPPC_D_22_I2C5_SDA_CRD2 */ + PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1), + /* D23 : GPPC_D_23_I2C5_SCL_CRD2 */ + PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1), + + /* E0 : IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF2), + /* E2 : IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), };
/* Early pad configuration in bootblock */ diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl new file mode 100644 index 0000000..0cfdd17 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/include/variant/acpi/camera.asl @@ -0,0 +1,15 @@ +/*This file is part of the coreboot project. + * + * Copyright 2020 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/camera.asl>