Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43303 )
Change subject: soc/amd/common: Use SPI settings from Kconfig options ......................................................................
soc/amd/common: Use SPI settings from Kconfig options
Since SPI speeds and mode are now set in Picasso Kconfig for EFS, remove duplicate values from device tree and instead harvest the values from Kconfig.
BUG=b:158755102 TEST=Read EFS values at appropriate offsets using a hex editor. Boot test on Tremblye and Morphius.
Change-Id: I765dada14700f4800263d2d3844af07fad0e5b71 Signed-off-by: Matt Papageorge matthewpapa07@gmail.com --- M src/mainboard/google/zork/variants/baseboard/devicetree.cb M src/soc/amd/common/block/include/amdblocks/chip.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi.c 4 files changed, 34 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43303/1
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree.cb b/src/mainboard/google/zork/variants/baseboard/devicetree.cb index 9db0d23..71c5b29 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree.cb @@ -138,15 +138,6 @@ .tx_res_tune = 0x01, }"
- # SPI Configuration - register "common_config.spi_config" = "{ - .normal_speed = SPI_SPEED_66M, /* MHz */ - .fast_speed = SPI_SPEED_66M, /* MHz */ - .altio_speed = SPI_SPEED_66M, /* MHz */ - .tpm_speed = SPI_SPEED_66M, /* MHz */ - .read_mode = SPI_READ_MODE_DUAL112, - }" - # eSPI Configuration register "common_config.espi_config" = "{ .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, diff --git a/src/soc/amd/common/block/include/amdblocks/chip.h b/src/soc/amd/common/block/include/amdblocks/chip.h index d150464..8835152 100644 --- a/src/soc/amd/common/block/include/amdblocks/chip.h +++ b/src/soc/amd/common/block/include/amdblocks/chip.h @@ -7,17 +7,6 @@ #include <amdblocks/spi.h>
struct soc_amd_common_config { - /* - * SPI configuration - * Default values if not overridden by mainboard: - * Read mode - Normal 33MHz - * Normal speed - 66MHz - * Fast speed - 66MHz - * Alt speed - 66MHz - * TPM speed - 66MHz - */ - struct spi_config spi_config; - /* eSPI configuration */ struct espi_config espi_config; }; diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index d226e0c..9773465 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -58,22 +58,6 @@ #define SPI_FIFO_LAST_BYTE 0xc7 #define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO)
-struct spi_config { - /* - * Default values if not overridden by mainboard: - * Read mode - Normal 33MHz - * Normal speed - 66MHz - * Fast speed - 66MHz - * Alt speed - 66MHz - * TPM speed - 66MHz - */ - enum spi_read_mode read_mode; - enum spi100_speed normal_speed; - enum spi100_speed fast_speed; - enum spi100_speed altio_speed; - enum spi100_speed tpm_speed; -}; - /* * Perform early SPI initialization: * 1. Sets SPI ROM base and enables SPI ROM diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index bf64c3f..5a1c945 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -49,16 +49,43 @@
static void fch_spi_config_mb_modes(void) { - const struct soc_amd_common_config *cfg = soc_get_common_config(); + uint8_t spi_speed = 0xff; + uint8_t spi_read_mode = 0xff;
- if (!cfg) - die("Common config structure is NULL!\n"); + if (CONFIG(SPI_SPEED_66M)) + spi_speed = SPI_SPEED_66M; + if (CONFIG(SPI_SPEED_33M)) + spi_speed = SPI_SPEED_33M; + if (CONFIG(SPI_SPEED_22M)) + spi_speed = SPI_SPEED_22M; + if (CONFIG(SPI_SPEED_16M)) + spi_speed = SPI_SPEED_16M; + if (CONFIG(SPI_SPEED_100M)) + spi_speed = SPI_SPEED_100M; + if (CONFIG(SPI_SPEED_800K)) + spi_speed = SPI_SPEED_800K;
- const struct spi_config *spi_cfg = &cfg->spi_config; + if (CONFIG(SPI_READ_MODE_NORMAL_33M)) + spi_read_mode = SPI_READ_MODE_NORMAL33M; + if (CONFIG(SPI_READ_MODE_DUAL_IO_112)) + spi_read_mode = SPI_READ_MODE_DUAL112; + if (CONFIG(SPI_READ_MODE_QUAD_IO_114)) + spi_read_mode = SPI_READ_MODE_QUAD114; + if (CONFIG(SPI_READ_MODE_DUAL_IO_122)) + spi_read_mode = SPI_READ_MODE_DUAL122; + if (CONFIG(SPI_READ_MODE_QUAD_IO_144)) + spi_read_mode = SPI_READ_MODE_QUAD144; + if (CONFIG(SPI_READ_MODE_NORMAL_66M)) + spi_read_mode = SPI_READ_MODE_NORMAL66M; + if (CONFIG(SPI_READ_MODE_FAST_READ)) + spi_read_mode = SPI_READ_MODE_FAST_READ;
- fch_spi_set_read_mode(spi_cfg->read_mode); - fch_spi_set_spi100(spi_cfg->normal_speed, spi_cfg->fast_speed, - spi_cfg->altio_speed, spi_cfg->tpm_speed); + if ((spi_speed == 0xff) || (spi_read_mode == 0xff)) + die("SPI configuration not properly set!\n"); + + fch_spi_set_read_mode(spi_read_mode); + fch_spi_set_spi100(spi_speed, spi_speed, + spi_speed, spi_speed); }
static void fch_spi_config_em100_modes(void)