Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47198 )
Change subject: mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47198/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/47198/5/src/mainboard/google/voltee... PS5, Line 418: so it can participate in power management.
Where does the power management happen? Is it in the OS (part of ACPI)? […]
I think because both root ports are part of the same UBS4 host controller they are both part of the power management flow, and the controller can't enter D3 until both root ports have been transitioned. (currently this all in static ASL for USB4/TBT)
There might be a way to make the PM work with coreboot disabling the port but when I tried it before the system failed to go into S0ix with errors, and I no longer have a TBT dock to test with so I'm wary to touch that ASL.