[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Lock down IIO DFX Global registers

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47447 )

Change subject: soc/intel/xeon_sp: Lock down IIO DFX Global registers
......................................................................

soc/intel/xeon_sp: Lock down IIO DFX Global registers

This is required for CbNT.

Change-Id: I565a95cd2e76cb1c648884be6d1954288f6e4804
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47447
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/mainboard/ocp/deltalake/devicetree.cb
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/uncore.c
4 files changed, 42 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb
index d51391d..06448c3 100644
--- a/src/mainboard/ocp/deltalake/devicetree.cb
+++ b/src/mainboard/ocp/deltalake/devicetree.cb
@@ -63,6 +63,9 @@
    	device pci 05.0 on end # Intel SkyLake-E MM/Vt-d Configuration Registers
    	device pci 05.2 on end # Intel SkyLake-E RAS
    	device pci 05.4 on end # Intel SkyLake-E IOAPIC
+		device pci 07.0 on end
+		device pci 07.4 on end
+		device pci 07.7 on end
    	device pci 08.0 on end # System peripheral: Intel SkyLake-E Ubox Registers
    	device pci 08.1 on end # Performance counters: Intel SkyLake-E Ubox Registers
    	device pci 08.2 on end # System peripheral: Intel SkyLake-E Ubox Registers
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index 6ddcce4..95290f2 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -127,4 +127,8 @@
 #define DMIRCBAR		0x50
 #define ERRINJCON		0x1d8

+// IIO DFX Global D7F7 registers
+#define IIO_DFX_TSWCTL0		0x30c
+#define IIO_DFX_LCK_CTL		0x504
+
 #endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 5fa2a38..02061f9 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -172,4 +172,8 @@
 #define DMIRCBAR		0x50
 #define ERRINJCON		0x1d8

+// IIO DFX Global D7F7 registers
+#define IIO_DFX_TSWCTL0		0x30c
+#define IIO_DFX_LCK_CTL		0x504
+
 #endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 2663023..7679f2f 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -374,3 +374,34 @@
    .vendor		= PCI_VENDOR_ID_INTEL,
    .device		= DMI3_DEVID,
 };
+
+static void iio_dfx_global_init(struct device *dev)
+{
+	uint16_t reg16;
+	pci_or_config16(dev, IIO_DFX_LCK_CTL, 0x3ff);
+	reg16 = pci_read_config16(dev, IIO_DFX_TSWCTL0);
+	reg16 &= ~(1 << 4); // allow ib mmio cfg
+	reg16 &= ~(1 << 5); // ignore acs p2p ma lpbk
+	reg16 |= (1 << 3); // me disable
+	pci_write_config16(dev, IIO_DFX_TSWCTL0, reg16);
+}
+
+static const unsigned short iio_dfx_global_ids[] = {
+	0x202d,
+	0x203d,
+	0
+};
+
+static struct device_operations iio_dfx_global_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= iio_dfx_global_init,
+	.ops_pci		= &soc_pci_ops,
+};
+
+static const struct pci_driver iio_dfx_global_driver __pci_driver = {
+	.ops		= &iio_dfx_global_ops,
+	.vendor		= PCI_VENDOR_ID_INTEL,
+	.devices	= iio_dfx_global_ids,
+};