Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35745 )
Change subject: soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default ......................................................................
soc/skylake/fsp: enable PCIe Advanced Error Reporting (AER) by default
PCIe Advanced Error Reporting (AER) povides better error reporting for PCIe devices/buses. This is enabled on most modern machines, so we should do the same and enable it by default.
Tested on X11SSM-F
Signed-off-by: Michael Niewöhner foss@mniewoehner.de Change-Id: I172329d8d42c3be02e64300675d646edfbee8b72 --- M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/soc/intel/skylake/chip_fsp20.c 11 files changed, 3 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35745/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 572cd6a..ed3cef8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -222,8 +222,6 @@ register "PcieRpClkReqSupport[5]" = "1" # Use SRCCLKREQ1# register "PcieRpClkReqNumber[5]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[5]" = "1" # Use CLK SRC 1 @@ -235,8 +233,6 @@ register "PcieRpClkReqSupport[4]" = "1" # Use SRCCLKREQ2# register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[4]" = "1" # Use CLK SRC 2 @@ -250,8 +246,6 @@ register "PcieRpClkReqSupport[6]" = "1" # Use SRCCLKREQ3# register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" # Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[6]" = "1" # Use CLK SRC 3 diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 50f9114..4669034 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -148,7 +148,6 @@ register "PcieRpEnable[0]" = "1" register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1" register "PcieRpHotPlug[0]" = "1" #RP 1 uses CLK SRC 1 @@ -158,7 +157,6 @@ register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1" #RP 5 uses CLK SRC 4 register "PcieRpClkSrcNumber[4]" = "4" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index c1afe3d..7a5ca10 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -187,8 +187,6 @@ register "PcieRpClkReqSupport[2]" = "1" # RP 3 uses SRCCLKREQ0# register "PcieRpClkReqNumber[2]" = "0" - # RP 3, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[2]" = "1" # RP 3, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[2]" = "1" # RP 3 uses uses CLK SRC 0 @@ -200,8 +198,6 @@ register "PcieRpClkReqSupport[3]" = "1" # RP 4 uses SRCCLKREQ5# register "PcieRpClkReqNumber[3]" = "5" - # RP 4, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[3]" = "1" # RP 4, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[3]" = "1" # RP 4 uses uses CLK SRC 5 @@ -213,8 +209,6 @@ register "PcieRpClkReqSupport[4]" = "1" # RP 5 uses SRCCLKREQ1# register "PcieRpClkReqNumber[4]" = "1" - # RP 5, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" # RP 5, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[4]" = "1" # RP 5 uses CLK SRC 1 @@ -226,8 +220,6 @@ register "PcieRpClkReqSupport[8]" = "1" # RP 9 uses SRCCLKREQ2# register "PcieRpClkReqNumber[8]" = "2" - # RP 9, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[8]" = "1" # RP 9, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[8]" = "1" # RP 9 uses uses CLK SRC 2 @@ -239,8 +231,6 @@ register "PcieRpClkReqSupport[10]" = "1" # RP 11 uses SRCCLKREQ2# register "PcieRpClkReqNumber[10]" = "2" - # RP 11, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[10]" = "1" # RP 11, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[10]" = "1" # RP 11 uses uses CLK SRC 2 @@ -252,8 +242,6 @@ register "PcieRpClkReqSupport[11]" = "1" # RP 12 uses SRCCLKREQ2# register "PcieRpClkReqNumber[11]" = "2" - # RP 12, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[11]" = "1" # RP 12, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[11]" = "1" # RP 12 uses uses CLK SRC 2 diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index ac86e79..27e9f48 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -151,7 +151,6 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1"
# USB 2.0 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index d960474..81c751a 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -147,8 +147,6 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" # RP 1 uses uses CLK SRC 1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 3d37eda..6656896 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -144,13 +144,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ1# # PcieRpClkSrcNumber: Uses 1 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[3]" = "1" register "PcieRpClkReqSupport[3]" = "1" register "PcieRpClkReqNumber[3]" = "1" register "PcieRpClkSrcNumber[3]" = "1" - register "PcieRpAdvancedErrorReporting[3]" = "1" register "PcieRpLtrEnable[3]" = "1"
# Root port 5 (x4) @@ -158,13 +156,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ3# # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[4]" = "1" register "PcieRpClkReqSupport[4]" = "1" register "PcieRpClkReqNumber[4]" = "3" register "PcieRpClkSrcNumber[4]" = "3" - register "PcieRpAdvancedErrorReporting[4]" = "1" register "PcieRpLtrEnable[4]" = "1"
# Root port 9 (x2) @@ -172,13 +168,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkSrcNumber: Uses 2 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "2" - register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 0 diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index ef5e8ad..f6212da 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -158,8 +158,6 @@ register "PcieRpClkReqNumber[0]" = "1" # RP 1 uses uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 75fcf9c..2bf4441 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -154,7 +154,6 @@ register "PcieRpClkReqSupport[0]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkSrcNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" register "PcieRpLtrEnable[0]" = "1"
# Root port 9 (x2) @@ -162,13 +161,11 @@ # PcieRpClkReqSupport: Enable CLKREQ# # PcieRpClkReqNumber: Uses SRCCLKREQ2# # PcieRpClkSrcNumber: Uses 3 - # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "1" register "PcieRpClkReqNumber[8]" = "2" register "PcieRpClkSrcNumber[8]" = "3" - register "PcieRpAdvancedErrorReporting[8]" = "1" register "PcieRpLtrEnable[8]" = "1"
# USB 2.0 diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 70a4667..2517282 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -147,8 +147,6 @@ register "PcieRpClkReqNumber[0]" = "1" # RP 1 uses uses CLK SRC 1 register "PcieRpClkSrcNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 4711b1f..3067849 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -147,8 +147,6 @@ register "PcieRpClkReqSupport[0]" = "1" # RP 1 uses SRCCLKREQ1# register "PcieRpClkReqNumber[0]" = "1" - # RP 1, Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[0]" = "1" # RP 1, Enable Latency Tolerance Reporting Mechanism register "PcieRpLtrEnable[0]" = "1" # RP 1 uses uses CLK SRC 1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index e46e52c..cb5f0e7 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -291,14 +291,14 @@ sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, sizeof(params->PcieRpClkReqNumber)); - memcpy(params->PcieRpAdvancedErrorReporting, - config->PcieRpAdvancedErrorReporting, - sizeof(params->PcieRpAdvancedErrorReporting)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug));
+ /* Enable PCIe Advanced Error Reporting for all root ports */ + memset(params->PcieRpAdvancedErrorReporting, 1, CONFIG_MAX_ROOT_PORTS); + /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for * all the enabled PCIe root ports, invalid(0x1F) is set for