[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Only use write Vref if supported

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47747 )

Change subject: nb/intel/sandybridge: Only use write Vref if supported
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nb/intel/sandybridge: Only use write Vref if supported

Only some Ivy Bridge SKUs support write Vref control.

Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/registers/host_bridge.h
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47747/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index d533ca8..01dfcc4 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -2459,6 +2459,13 @@
    int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
    int channel, slotrank, lane;

+	/* Changing the write Vref is only supported on some Ivy Bridge SKUs */
+	if (!IS_IVY_CPU(ctrl->cpu))
+		return 0;
+
+	if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF))
+		return 0;
+
    FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES {
    	lower[channel][slotrank][lane] = 0;
    	upper[channel][slotrank][lane] = MAX_TIMC;
diff --git a/src/northbridge/intel/sandybridge/registers/host_bridge.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h
index 4814b94..9599871 100644
--- a/src/northbridge/intel/sandybridge/registers/host_bridge.h
+++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h
@@ -52,6 +52,7 @@
 #define  CAPID_ECCDIS	(1 << 25)
 #define  CAPID_DDPCD	(1 << 14)
 #define  CAPID_PDCD	(1 << 12)
+#define  CAPID_WRTVREF	(1 <<  1)
 #define  CAPID_DDRSZ(x)	(((x) >> 19) & 0x3)

#define CAPID0_B	0xe8	/* Capabilities Register B */