Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7245
-gerrit
commit 3398491774c93c7b440e343bacef05947ae77de4 Author: Bruce Griffith Bruce.Griffith@se-eng.com Date: Wed Oct 29 02:01:24 2014 -0600
AMD Hudson: Add Avalon to southbridge #idefs in imc.c
The #ifdefs in imc.c are missing the Avalon config variable. It isn't currently used because IMC support is disabled for all curent Steppe Eagle boards. But this fixes the #ifdef for when IMC is enabled for Olive Hill+ sometime in the future and makes the code match Kabini.
Change-Id: I7cc765b70568f759fe4289ae270c4f1571fdfa20 Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com --- src/southbridge/amd/agesa/hudson/imc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index d706292..7ab2f54 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -37,7 +37,7 @@ void imc_reg_init(void) write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x03, 0xff); write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x04, 0xff);
-#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE && !CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x10, 0x06); write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x11, 0x06); write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x12, 0xf7); @@ -45,7 +45,7 @@ void imc_reg_init(void) write8(ACPI_MMIO_BASE + PMIO2_BASE + 0x14, 0xff); #endif
-#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE || CONFIG_SOUTHBRIDGE_AMD_AGESA_AVALON UINT8 PciData; PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader;