Marc Jones (marc@marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18436
-gerrit
commit 9b31653ed3290b79fc5f6709d8c46124c023a771 Author: Marshall Dawson marshalldawson3rd@gmail.com Date: Sun Feb 12 10:31:15 2017 -0700
amd/pi/hudson: Move APIC enable to CPU file
Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used.
This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y.
The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n.
Original-Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Original-Reviewed-by: Marc Jones marcj303@gmail.com (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad)
Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones marcj303@gmail.com --- src/cpu/amd/pi/00630F01/fixme.c | 6 ++++++ src/cpu/amd/pi/00660F01/fixme.c | 6 ++++++ src/cpu/amd/pi/00670F00/fixme.c | 6 ++++++ src/cpu/amd/pi/00730F01/fixme.c | 6 ++++++ src/southbridge/amd/pi/hudson/early_setup.c | 4 ---- 5 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index fcdc925..e33a3c9 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -77,4 +77,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 973b0a7..fb1dfd7 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -85,6 +85,12 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif }
unsigned long car_bist_mask_bist(unsigned long bist) diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 5e9ac79..3f02d7a 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -89,6 +89,12 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif }
unsigned long car_bist_mask_bist(unsigned long bist) diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index fcdf498..f6405a5 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -89,4 +89,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + +#if IS_ENABLED(CONFIG_UDELAY_LAPIC) + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); +#endif } diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 32abaff..a650468 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -35,12 +35,8 @@
void configure_hudson_uart(void) { - msr_t msr; u8 byte;
- msr = rdmsr(0x1B); - msr.lo |= 1 << 11; - wrmsr(0x1B, msr); byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); byte |= 1 << 3; write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte);