Attention is currently required from: Angel Pons, Keith Hui.
Nicholas Chin has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ......................................................................
Patch Set 6:
(1 comment)
Patchset:
PS6:
After rebuilding PS 6 and reprogramming the flash with an external programmer, PS 6 becomes stabler, […]
I see that the ASM1061 is detected in the PS 4 log. In the log for PS 6, the chipset does seem to know that something is connected to root port 3, but isn't able to enumerate it: ``` [DEBUG] PCI: 00:00:1c.3 scanning... [DEBUG] PCI: pci_scan_bus for segment group 00 bus 03 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port [WARN ] PCI: 00:00:1c.3: Has a slow downstream device. Enumeration failed. [DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs ``` As far as I can tell the GPIO 5 levels for each mode are correct, and setting them to push pull is also correct. The only other thing I can think is doing some sort of soft reset of the system after setting the GPIOs such that the SuperIO doesn't get reset and maintains the output states. Perhaps switching the PCIe muxes at runtime makes the chipset or card unhappy without resetting the bus.