Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4859
-gerrit
commit 6eea57dbd6dc4cb1304dbdfa9e2736fd89704c03 Author: Aaron Durbin adurbin@chromium.org Date: Thu Oct 3 08:57:17 2013 -0500
baytrail: additional iosf changes
Allow for one to write an individual byte of a 32-bit register when sending a read/write through the IOSF messaging system. Add PUNIT registers and fields for early sequencing.
BUG=chrome-os-partner:23085 BRANCH=None TEST=Built and partially booted with changes that use PUNIT registers and individual byte en fields.
Change-Id: I929fb5c51d805c55c478cab884e3572254987fc7 Signed-off-by: Aaron Durbin adurbin@chromium.org Reviewed-on: https://chromium-review.googlesource.com/171710 Reviewed-by: Duncan Laurie dlaurie@chromium.org --- src/soc/intel/baytrail/baytrail/iosf.h | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 444dc38..b1f28da 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -45,7 +45,12 @@ #define IOSF_OPCODE(x) ((x) << 24) #define IOSF_PORT(x) ((0xff & (x)) << 16) #define IOSF_REG(x) ((0xff & (x)) << 8) -#define IOSF_BYTE_EN 0xf0 +#define IOSF_BYTE_EN_0 0x10 +#define IOSF_BYTE_EN_1 0x20 +#define IOSF_BYTE_EN_2 0x40 +#define IOSF_BYTE_EN_3 0x80 +#define IOSF_BYTE_EN \ + (IOSF_BYTE_EN_0 | IOSF_BYTE_EN_1 | IOSF_BYTE_EN_2 | IOSF_BYTE_EN_3) #define MDR_REG 0xd4 #define MCRX_REG 0xd8
@@ -124,4 +129,22 @@ void iosf_dunit_write(int reg, uint32_t val); # define DTR0_SPEED_1333 0x02 # define DTR0_SPEED_1600 0x03
+/* + * PUNIT Registers + */ +#define SB_BIOS_CONFIG 0x06 +# define SB_BIOS_CONFIG_ECC_EN (1 << 31) +# define SB_BIOS_CONFIG_DUAL_CH_DIS (1 << 30) +# define SB_BIOS_CONFIG_EFF_ECC (1 << 29) +# define SB_BIOS_CONFIG_EFF_DUAL_CH_DIS (1 << 28) +# define SB_BIOS_CONFIG_PERF_MODE (1 << 17) +# define SB_BIOS_CONFIG_PDM_MODE (1 << 16) +# define SB_BIOS_CONFIG_DDRIO_PWRGATE (1 << 8) +# define SB_BIOS_CONFIG_GFX_TURBO_DIS (1 << 7) +# define SB_BIOS_CONFIG_PCIE_PLLOFFOK (1 << 1) +# define SB_BIOS_CONFIG_USB_CACHING_EN (1 << 0) +#define BIOS_RESET_CPL 0x05 +# define BIOS_RESET_CPL_ALL_DONE (1 << 1) +# define BIOS_RESET_CPL_RESET_DONE (1 << 0) + #endif /* _BAYTRAIL_IOSF_H_ */