[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel: Fix slp-s0 residency counter frequency LPIT table

[Kapil Porwal (Code Review)]

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Lance Zhao, Subrata Banik, Sukumar Ghorai, Tarun, Tim Wawrzynczak.

Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78164?usp=email )

Change subject: soc/intel: Fix slp-s0 residency counter frequency LPIT table
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Patch Set 7:

(2 comments)

File src/acpi/Kconfig:

https://review.coreboot.org/c/coreboot/+/78164/comment/1743fc3d_d5d896a9 :
PS7, Line 95: config ACPI_SOC_INTEL_SLP_S0_FREQ_VALUE
            : 	bool
            : 	help
            : 	 Selected by platforms that slp_s0 freq is varies in different Intel SoC
            : 
can we use below config instead -

```
config ACPI_SOC_INTEL_SLP_S0_FREQ
    hex
    default 0x0
    help
      slp_s0_residency counter runs at TSC frequency.
```

File src/include/acpi/acpi.h:

https://review.coreboot.org/c/coreboot/+/78164/comment/b1ff83cd_8d0ef960 :
PS4, Line 456: _TSC
> yes, refer https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_I..., […]

In that case, also rename the macro from `ACPI_LPIT_CTR_FREQ_TSC` to `ACPI_LPIT_CTR_FREQ`.