[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Enable TCSS USB ports

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54330 )

Change subject: mb/google/brya: Enable TCSS USB ports
......................................................................

mb/google/brya: Enable TCSS USB ports

This patch enables TCSS USB ports and undo the workaround to enable the
TCSS USB ports.

TEST=Verified on brya
BUG=b:184324979
DEPENDS ON=FSPv2172

Signed-off-by: Sridhar Siricilla 
Change-Id: Ibb4f3f4ce154c73d766df21079c1a9ad8bfc2f0d
---
M src/mainboard/google/brya/variants/baseboard/devicetree.cb
1 file changed, 3 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/54330/1

diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
index 5f73671..07ef897 100644
--- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb
@@ -17,6 +17,9 @@
         # S0ix enable
         register "s0ix_enable" = "1"

+	# TCSS USB port enable
+	register "UsbTcPortEn" = "0x7"
+
    # DPTF enable
    register "dptf_enable" = "1"

@@ -50,12 +53,6 @@
    register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
-	# TODO(b/184324979): Workaround to enable TCSS ports. FSP v2081
-	# uses port enable for south XHCI ports to determine if TCSS
-	# ports should be enabled. Until FSP is fixed, enable south
-	# XHCI ports 1 and 2.
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"
-	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"
    register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"