Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79940?usp=email )
Change subject: mb/lenovo/x220: Remove superfluous comments related to PCI devices ......................................................................
mb/lenovo/x220: Remove superfluous comments related to PCI devices
Since all devicetrees from lenovo/x220 are using the reference names for PCI devices now, remove the equivalent comments documenting their function.
Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x220/variants/x1/overridetree.cb M src/mainboard/lenovo/x220/variants/x220/overridetree.cb 3 files changed, 33 insertions(+), 33 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 866d6c3..233f690 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -38,9 +38,9 @@ device domain 0 on subsystemid 0x17aa 0x21db inherit
- device ref host_bridge on end # host bridge - device ref peg10 off end # PCIe Bridge for discrete graphics - device ref igd on end # vga controller + device ref host_bridge on end + device ref peg10 off end + device ref igd on end
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -68,37 +68,37 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005"
- device ref mei1 on end # Management Engine Interface 1 - device ref mei2 off end # Management Engine Interface 2 - device ref me_ide_r off end # Management Engine IDE-R - device ref me_kt off end # Management Engine KT + device ref mei1 on end + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end device ref gbe on subsystemid 0x17aa 0x21ce - end # Intel Gigabit Ethernet - device ref ehci2 on end # USB2 EHCI #2 - device ref hda on end # High Definition Audio - device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp2 on # PCIe Port #2 (wlan) + end + device ref ehci2 on end + device ref hda on end + device ref pcie_rp1 off end + device ref pcie_rp2 on smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort" "WIFI" "SlotDataBusWidth1X" end - device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp3 off end device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 + end device ref pcie_rp5 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end - end # PCIe Port #5 (SD) - device ref pcie_rp6 off end # PCIe Port #6 - device ref pcie_rp7 on end # PCIe Port #7 Optional XHCI controller - device ref pcie_rp8 off end # PCIe Port #8 - device ref ehci1 on end # USB2 EHCI #1 - device ref pci_bridge off end # PCI bridge - device ref lpc on #LPC bridge + end + device ref pcie_rp6 off end + device ref pcie_rp7 on end # Optional XHCI controller + device ref pcie_rp8 off end + device ref ehci1 on end + device ref pci_bridge off end + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "true" @@ -149,8 +149,8 @@ register "wwan_gpio_num" = "70" register "wwan_gpio_lvl" = "0" end - end # LPC bridge - device ref sata1 on end # SATA Controller 1 + end + device ref sata1 on end device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c @@ -163,9 +163,9 @@ device i2c 5e on end device i2c 5f on end end - end # SMBus - device ref sata2 off end # SATA Controller 2 - device ref thermal on end # Thermal + end + device ref sata2 off end + device ref thermal on end end end end diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index 2defac8..bf88150 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -21,10 +21,10 @@ # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- device ref pcie_rp1 off end # PCIe Port #1 - device ref pcie_rp3 off end # PCIe Port #3 - device ref pcie_rp4 off end # PCIe Port #4 - device ref lpc on #LPC bridge + device ref pcie_rp1 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config2" = "0xe0" @@ -36,7 +36,7 @@ register "event5_enable" = "0x3c" register "evente_enable" = "0x3d" end - end # LPC bridge + end end end end diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index 9325480..b9caa25 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,13 +1,13 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device ref lpc on #LPC bridge + device ref lpc on chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "eventa_enable" = "0x01" register "eventb_enable" = "0xf0" end - end # LPC bridge + end end end end