Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40335 )
Change subject: src/arch/x86/acpi: Increase Max PCI bus count support ......................................................................
Patch Set 1:
(3 comments)
I'm curious if there really are SoCs yet with multiple PCI segments? Is this commit series just for preparation or is there already a use case?
I don't think it's really needed and wonder if we can't normalize on 256MiB instead? All current SoCs seem to use that. Also, values >=2GiB naturally can't work with FSP, because it forces us into 32-bit mode.
https://review.coreboot.org/c/coreboot/+/40335/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/40335/1//COMMIT_MSG@10 PS1, Line 10: SoC specification [Ice Lake EDS vol 1 chapter 3.18] ICL can address multiple PCI segments, but does it really have them?
https://review.coreboot.org/c/coreboot/+/40335/1//COMMIT_MSG@10 PS1, Line 10: 1 vol 2?
https://review.coreboot.org/c/coreboot/+/40335/1/src/arch/x86/acpi.c File src/arch/x86/acpi.c:
https://review.coreboot.org/c/coreboot/+/40335/1/src/arch/x86/acpi.c@114 PS1, Line 114: end_bus_number This is `u8` too and we can't change it. Having more than 256 buses means that there is more than one PCI segment, and this function should be called for each.