[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Patrick Rudolph.
Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56010 )

Change subject: soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine
......................................................................

soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine

The pep.asl file is being obsoleted by runtime generation, therefore
switch cannonlake boards to this method.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Ic5343b0fd37eafac29a23846c8cfc3ca93d1821d
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/acpi/southbridge.asl
M src/soc/intel/cannonlake/pmc.c
3 files changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/56010/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 5fc80af..68c5933 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -81,6 +81,7 @@
    select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC
    select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO
    select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT
+	select SOC_INTEL_COMMON_BLOCK_ACPI_PEP
    select SOC_INTEL_COMMON_BLOCK_CAR
    select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
    select SOC_INTEL_COMMON_BLOCK_CNVI
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index fa75673..052847d 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -39,6 +39,3 @@

/* GbE 0:1f.6 */
 #include <soc/intel/common/block/acpi/acpi/pch_glan.asl>
-
-/* Intel Power Engine Plug-in */
-#include <soc/intel/common/block/acpi/acpi/pep.asl>
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index 59f4be5..a8e63e4 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <device/mmio.h>
 #include <device/device.h>
+#include <intelblocks/acpi.h>
 #include <intelblocks/pmc.h>
 #include <intelblocks/pmclib.h>
 #include <intelblocks/rtc.h>
@@ -124,5 +125,8 @@
    .set_resources	  = noop_set_resources,
    .init		  = soc_acpi_mode_init,
    .enable		  = pmc_init,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.acpi_fill_ssdt	  = generate_acpi_power_engine,
+#endif
    .scan_bus	  = scan_static_bus,
 };