Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35035 )
Change subject: arch/x86: Implement RESET_VECTOR_IN_RAM for bootblock ......................................................................
Patch Set 12:
(5 comments)
https://review.coreboot.org/c/coreboot/+/35035/1/src/arch/x86/early_dram.ld File src/arch/x86/early_dram.ld:
https://review.coreboot.org/c/coreboot/+/35035/1/src/arch/x86/early_dram.ld@... PS1, Line 27: _car_stack_start = .;
There is probably some easy way to put this in between _program and _eprogram. Section . […]
Resolving - stale now.
https://review.coreboot.org/c/coreboot/+/35035/1/src/arch/x86/early_dram.ld@... PS1, Line 35: PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
If we have some CBMEM console before romstage, it would be from PSP execution. […]
Resolving - stale now.
https://review.coreboot.org/c/coreboot/+/35035/1/src/arch/x86/early_dram.ld@... PS1, Line 37: TIMESTAMP(., 0x200)
Same thing with timestamps. […]
Resolving - stale now.
https://review.coreboot.org/c/coreboot/+/35035/1/src/arch/x86/early_dram.ld@... PS1, Line 42: _car_ehci_dbg_info_end = .;
Can be removed. This was to support usbdebug more smoothly thru bootblock and verstage. […]
Done
https://review.coreboot.org/c/coreboot/+/35035/6/src/arch/x86/include/arch/c... File src/arch/x86/include/arch/cpu.h:
https://review.coreboot.org/c/coreboot/+/35035/6/src/arch/x86/include/arch/c... PS6, Line 298: asmlinkage void soc_hybrid_romstage_entry(uint32_t bist, uint64_t early_tsc);
In the case of early_tsc, it's not too different than with the bootblock arrangement, i.e. […]
Not passing tsc but keeping bist.