Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889
-gerrit
commit 7821345d55e5029447bd1f99e71d855b206f3fbb Author: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Date: Thu Dec 15 19:29:51 2016 +0530
skylake: Restore target offset value after exiting from S3
Before entering in S3, the target offset value is 10 degree C. After exiting from S3, Coreboot is not restoring the target offset value and it is setting it to the default value as 0. With the default target offset value as 0 and target temperature Tjmax value as 100 degree C, Pcode firmware starts taking prochot action at 100 degree C [Tjmax-Offset]. But before Pcode firmware starts prochot action at 100 degree C, device is getting shutdown at 99 degree C due to DPTF critical CPU temperature after exiting from S3. So, this patch restores the target offset value after exiting from S3.
BUG=chrome-os-partner:59397 BRANCH=None. TEST=Built for skylake platform and verified the target offset value before and after S3.
Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- src/soc/intel/skylake/cpu.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 3ec8d2c..0458a93 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -206,6 +206,8 @@ static void configure_thermal_target(void) wrmsr(MSR_TEMPERATURE_TARGET, msr); } msr = rdmsr(MSR_TEMPERATURE_TARGET); + msr.lo &= ~(0xf << 24); /* Bits 27:24 */ + msr.lo |= 0xa << 24; /* set target offset as 10 degree C */ msr.lo &= ~0x7f; /* Bits 6:0 */ msr.lo |= 0xe6; /* setting 100ms thermal time window */ wrmsr(MSR_TEMPERATURE_TARGET, msr);