[coreboot-gerrit] [XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K

[Jarried Lin (Code Review)]

Attention is currently required from: Jarried Lin.

Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85094?usp=email

to look at the new patch set (#2).

Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
......................................................................

mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K

Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will
enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the
FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is
larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge
RW_MRC_CACHE from 8K to 16K.

TEST=Build pass
BUG=b:317009620

Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e
Signed-off-by: Jarried Lin 
---
M src/mainboard/google/rauru/chromeos.fmd
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/85094/2